NETWORK ON CHIP
Dennard scaling has stopped and Moore's law is also on the verge of end. In such a scenario better management of on-chip resources is the key for high performant and energy efficient architecture. Coming up with innovative interconnection design, while keeping in mind the limitations and constraints introduced by underlying circuit-technology and software stack running on it, incites me.
I am interested in both on-Chip and off-chip memory management. On-chip caches in particular interests me. With upcoming many-core architectures (Many-Core CPUs, GPUs, Neural Networks) management of on-chip memory is becoming exceedingly crucial.